ORCID Profile
0000-0002-3242-8197
Current Organisation
University of Adelaide
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In Research Link Australia (RLA), "Research Topics" refer to ANZSRC FOR and SEO codes. These topics are either sourced from ANZSRC FOR and SEO codes listed in researchers' related grants or generated by a large language model (LLM) based on their publications.
Electrical and Electronic Engineering | Other Electronic Engineering | Interdisciplinary Engineering Not Elsewhere Classified | Biomedical Engineering Not Elsewhere Classified | Interdisciplinary Engineering | Microelectronics and Integrated Circuits | Control Systems, Robotics and Automation | Decision Support and Group Support Systems | Communications Technologies | Electrical and Electronic Engineering not elsewhere classified | Mineral Processing/Beneficiation | Polymers and Plastics | Mechanical Engineering | Microelectromechanical Systems (MEMS) | Antennas and Propagation | Microwave and Millimetrewave Theory and Technology
Biological sciences | Physical sciences | Expanding Knowledge in Technology | Communication Equipment not elsewhere classified | Medical instrumentation | Scientific instrumentation | Expanding Knowledge in the Chemical Sciences | Expanding Knowledge in Engineering | Integrated Circuits and Devices | Beneficiation or Dressing of Iron Ores | Integrated Systems | Mining and Extraction of Precious (Noble) Metal Ores | Mining and Extraction of Copper Ores |
Publisher: SPIE
Date: 11-2002
DOI: 10.1117/12.469667
Publisher: IOP Publishing
Date: 23-12-2011
Publisher: IEEE
Date: 02-2012
Publisher: Wiley
Date: 07-01-2014
DOI: 10.1002/CTA.1893
Publisher: IOP Publishing
Date: 18-03-2009
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 03-2014
Publisher: IEEE
Date: 06-2012
Publisher: SPIE
Date: 21-12-2008
DOI: 10.1117/12.759762
Publisher: IEEE
Date: 04-2010
Publisher: SPIE
Date: 26-12-2008
DOI: 10.1117/12.813924
Publisher: IEEE
Date: 2011
Publisher: IEEE
Date: 09-2010
Publisher: IEEE
Date: 09-2011
Publisher: SPIE
Date: 30-03-2004
DOI: 10.1117/12.521414
Publisher: IEEE
Date: 12-2012
Publisher: SPIE
Date: 21-12-2008
DOI: 10.1117/12.769202
Publisher: SPIE
Date: 21-12-2008
DOI: 10.1117/12.764795
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 03-2012
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 04-2023
Publisher: SPIE
Date: 21-12-2008
DOI: 10.1117/12.765011
Publisher: IEEE
Date: 2000
Publisher: IEEE
Date: 10-2011
Publisher: Elsevier BV
Date: 12-2002
Publisher: IEEE
Date: 06-2012
Publisher: SPIE
Date: 27-12-2007
DOI: 10.1117/12.695580
Publisher: Springer Science and Business Media LLC
Date: 04-08-2015
DOI: 10.1038/SREP12785
Abstract: Physical unclonable functions (PUFs) exploit the intrinsic complexity and irreproducibility of physical systems to generate secret information. The advantage is that PUFs have the potential to provide fundamentally higher security than traditional cryptographic methods by preventing the cloning of devices and the extraction of secret keys. Most PUF designs focus on exploiting process variations in Complementary Metal Oxide Semiconductor (CMOS) technology. In recent years, progress in nanoelectronic devices such as memristors has demonstrated the prevalence of process variations in scaling electronics down to the nano region. In this paper, we exploit the extremely large information density available in nanocrossbar architectures and the significant resistance variations of memristors to develop an on-chip memristive device based strong PUF (mrSPUF). Our novel architecture demonstrates desirable characteristics of PUFs, including uniqueness, reliability and large number of challenge-response pairs (CRPs) and desirable characteristics of strong PUFs. More significantly, in contrast to most existing PUFs, our PUF can act as a reconfigurable PUF (rPUF) without additional hardware and is of benefit to applications needing revocation or update of secure key information.
Publisher: IEEE
Date: 04-2010
Publisher: SPIE
Date: 21-12-2011
DOI: 10.1117/12.902754
Publisher: SPIE
Date: 27-12-2007
DOI: 10.1117/12.695743
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 04-2013
Publisher: SPIE
Date: 21-12-2008
DOI: 10.1117/12.758726
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 08-2014
Publisher: IEEE
Date: 06-2012
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 06-2012
Publisher: IEEE
Date: 08-2011
Publisher: SPIE
Date: 28-02-2005
DOI: 10.1117/12.609912
Publisher: SPIE
Date: 11-2002
DOI: 10.1117/12.472851
Publisher: SPIE
Date: 27-03-2008
DOI: 10.1117/12.790789
Publisher: SPIE
Date: 23-04-2003
DOI: 10.1117/12.497792
Publisher: IEEE
Date: 12-2011
Publisher: Springer Berlin Heidelberg
Date: 2009
Publisher: Public Library of Science (PLoS)
Date: 30-09-2014
Publisher: IEEE Comput. Soc
Date: 2004
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2020
Publisher: SPIE
Date: 26-12-2008
DOI: 10.1117/12.814074
Publisher: Springer Netherlands
Date: 2011
Publisher: IEEE
Date: 12-2007
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 1998
DOI: 10.1109/96.659500
Publisher: IEEE
Date: 04-2015
Publisher: SPIE
Date: 21-11-2001
DOI: 10.1117/12.449155
Publisher: SPIE
Date: 28-02-2005
DOI: 10.1117/12.582318
Publisher: IEEE
Date: 09-2014
Publisher: Springer Science and Business Media LLC
Date: 24-02-2020
Publisher: IEEE
Date: 12-2006
Publisher: IEEE
Date: 2009
Publisher: Elsevier BV
Date: 10-2023
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 12-2018
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 09-2012
Publisher: IOP Publishing
Date: 22-04-2013
Publisher: Springer Berlin Heidelberg
Date: 2009
Publisher: IEEE
Date: 07-2012
Publisher: Royal Society of Chemistry (RSC)
Date: 2019
DOI: 10.1039/C9RA07481C
Abstract: In this study, a bio-fabrication method has been developed for the preparation of 3D graphene–alginate composite scaffolds with great potential for neural tissue engineering.
Publisher: IOP Publishing
Date: 31-08-2011
Publisher: SPIE
Date: 30-03-2004
DOI: 10.1117/12.524776
Publisher: Institution of Engineering and Technology (IET)
Date: 2010
DOI: 10.1049/EL.2010.1775
Publisher: SPIE
Date: 28-02-2005
DOI: 10.1117/12.580705
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 09-2015
Publisher: American Scientific Publishers
Date: 05-2013
Abstract: A simple method for the synthesis of Pt-Pd nanocatalysts was developed for a proton-exchange membrane fuel cell (PEMFC), which was loaded on a nafion coated carbon black via the sequential reduction of palladium(II) bis(acetylacetonato) and platinum(II) bis(acetylacetonato) in a drying process. Metallic precursors were sublimed and reduced on a nafion coated carbon black which was spray coated on a gas diffusion layer (GDL) in a glass reactor of N2 atmosphere at 180 degrees C for various times. The morphology and distribution of the Pt and Pd nanoparticles were observed by scanning electron microscopy (SEM) and transmission electron microscopy (TEM), and we found that the loading weight, number density and particle size of Pt-Pd nanoparticles increased with increasing exposure time at 180 degrees C.
Publisher: AIP Publishing
Date: 26-08-2014
DOI: 10.1063/1.4893751
Abstract: This article presents an analysis of metamaterial resonators coupled with microstrip transmission line. The behavior of complementary electric-LC resonators loaded on a microstrip line is analyzed using the equivalent circuit model. In this paper, it is shown that a special type of these resonators show a dual-mode behavior when excited through the electromagnetic field around the microstrip transmission lines. The bandstop and bandpass configurations of these dual mode resonators loaded with microstrip lines are introduced and analyzed. Their potential applications are highlighted through designing a displacement sensor and a dual-mode bandpass filter prototypes.
Publisher: IEEE
Date: 11-2013
Publisher: IOP Publishing
Date: 04-05-2005
Publisher: SPIE
Date: 27-12-2007
DOI: 10.1117/12.696106
Publisher: SPIE
Date: 21-11-2001
DOI: 10.1117/12.449171
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 05-2014
Publisher: Hindawi Limited
Date: 24-10-2015
DOI: 10.1002/ETEP.1814
Publisher: Institution of Engineering and Technology (IET)
Date: 2001
DOI: 10.1049/EL:20010742
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 06-2019
Publisher: SPIE
Date: 21-04-2003
DOI: 10.1117/12.501209
Publisher: IEEE
Date: 03-2014
Publisher: Inderscience Publishers
Date: 2010
Publisher: Inderscience Publishers
Date: 2010
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2023
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2023
Publisher: SPIE
Date: 11-2002
DOI: 10.1117/12.476427
Publisher: Springer International Publishing
Date: 2015
Publisher: IEEE
Date: 11-2008
Publisher: SPIE
Date: 26-12-2009
DOI: 10.1117/12.810602
Publisher: Institution of Engineering and Technology (IET)
Date: 2000
DOI: 10.1049/EL:20000384
Publisher: SPIE
Date: 23-04-2003
DOI: 10.1117/12.498597
Publisher: IEEE
Date: 04-2013
Publisher: IOP Publishing
Date: 06-08-2009
Publisher: SPIE
Date: 27-12-2007
DOI: 10.1117/12.695700
Publisher: American Scientific Publishers
Date: 05-2013
Abstract: This paper introduces an integrated sensor circuit based on an analog Memristor-MOS (M2) pattern matching building block that calculates the similarity/dissimilarity between two analog values. A new approach for a pulse-width modulation pixel image sensor compatible with the memristive-MOS matching structure is introduced allowing direct comparison between incoming and stored images. The pulsed-width encoded information from the pixels is forwarded to a matching circuitry that provides an anti-Gaussian-like comparison between the states of memristors. The non-volatile and multi-state memory characteristics of memristor, together with the related ability to be programmed at any one of the intermediate states between logic '1' and logic '0' brings us closer to the implementation of bio-machines that can eventually emulate human-like sensory functions.
Publisher: IEEE
Date: 2009
Publisher: Elsevier BV
Date: 12-2002
Publisher: SPIE
Date: 16-03-2001
DOI: 10.1117/12.418773
Publisher: Institution of Engineering and Technology (IET)
Date: 2002
DOI: 10.1049/EL:20020687
Publisher: American Scientific Publishers
Date: 05-2013
Abstract: This paper proposes a programmable inhibitory interconnection network between pixels in an array of novel low-voltage Schmitt-trigger-based PFM sensors that will be of interest for future applications in memristor-based early vision processing. In addition, a new low-power inverter-based pulse-frequency modulation (PFM) design and its integration with the network is also presented. To ensure no change in the memristors conductance in the network, the CMOS imager was designed for low voltage operation. That has resulted in a significant power reduction, better than 60%, and a comparable linear dynamic range when compared to published designs in the literature. The design was performed using a 0.13 um Samsung Electronics standard CMOS process, using 0.75 V supply voltage.
Publisher: IEEE
Date: 06-2010
Publisher: Institution of Engineering and Technology (IET)
Date: 06-2013
DOI: 10.1049/EL.2013.1010
Publisher: Springer Science and Business Media LLC
Date: 16-03-2017
Publisher: IEEE
Date: 12-2013
Publisher: IEEE
Date: 05-2015
Publisher: Hindawi Limited
Date: 27-06-2019
Publisher: Institution of Engineering and Technology (IET)
Date: 2003
DOI: 10.1049/EL:20030056
Publisher: SPIE
Date: 30-03-2004
DOI: 10.1117/12.530180
Publisher: IOP Publishing
Date: 17-01-2008
Publisher: The Royal Society
Date: 17-03-2010
Abstract: In 2008, researchers at the Hewlett–Packard (HP) laboratories published a paper in Nature reporting the development of a new basic circuit element that completes the missing link between charge and flux linkage, which was postulated by Chua in 1971 (Chua 1971 IEEE Trans. Circuit Theory 18 , 507–519 ( doi:10.1109/TCT.1971.1083337 )). The HP memristor is based on a nanometre scale TiO 2 thin film, containing a— doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and non-volatile RAM, they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application-specific integrated circuits and field programmable gate arrays. A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for integrated circuits. This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell’s equations. We also review Chua’s arguments based on electromagnetic theory.
Publisher: SPIE
Date: 28-12-2006
DOI: 10.1117/12.638310
Publisher: Institution of Engineering and Technology (IET)
Date: 2002
DOI: 10.1049/EL:20020438
Publisher: IEEE Comput. Soc
Date: 2004
Publisher: IEEE
Date: 09-2012
Publisher: SPIE
Date: 30-03-2004
DOI: 10.1117/12.522049
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 05-2014
Publisher: Elsevier BV
Date: 09-2013
DOI: 10.1016/J.NEUNET.2013.03.003
Abstract: Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.
Publisher: SPIE
Date: 27-12-2006
DOI: 10.1117/12.696294
Publisher: IEEE
Date: 12-2011
Publisher: IEEE
Date: 10-2013
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 07-2021
Publisher: IEEE
Date: 05-2014
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 09-2023
Publisher: SPIE
Date: 27-03-2008
DOI: 10.1117/12.790608
Publisher: IEEE
Date: 11-2008
Start Date: 2003
End Date: 12-2004
Amount: $50,000.00
Funder: Australian Research Council
View Funded ActivityStart Date: 10-2022
End Date: 10-2024
Amount: $580,000.00
Funder: Australian Research Council
View Funded ActivityStart Date: 2005
End Date: 12-2013
Amount: $198,000.00
Funder: Australian Research Council
View Funded ActivityStart Date: 2012
End Date: 12-2016
Amount: $320,000.00
Funder: Australian Research Council
View Funded ActivityStart Date: 08-2020
End Date: 08-2026
Amount: $3,703,664.00
Funder: Australian Research Council
View Funded ActivityStart Date: 05-2005
End Date: 12-2006
Amount: $864,610.00
Funder: Australian Research Council
View Funded Activity