ORCID Profile
0000-0002-0799-500X
Current Organisation
National University of Singapore
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Publisher: Hindawi Limited
Date: 07-09-2020
Publisher: Wiley
Date: 28-03-2022
DOI: 10.1002/CTA.3279
Abstract: An active neutral point cl ed‐type multilevel inverter (ANPC‐MLI) with self‐voltage balancing capability is being suggested for this study. A new switched capacitor cell with eight switches is used for seven‐level generation in the proposed topology. The topology proposed has decreased the power element count with the ability to self‐balancing of capacitor voltages and boosting ability. The distinguishing characteristics of the proposed topology are emphasized and compared with other recent 7L‐SCMLI topologies. Experimental testing on a prototype hardware is conducted to validate the feasibility of the proposed topology.
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2020
Publisher: MDPI AG
Date: 16-10-2020
DOI: 10.3390/ELECTRONICS9101703
Abstract: The recent advancement in the application of the internet of things in the smart grid has led to an industrial revolution in the power industry. The Industry 4.0 revolution has already set in, allowing computers to interact for an efficient and intelligent approach in solving smart grid issues. multilevel inverters (MLIs) are an integral part of the smart grid system for integrating the distributed generation sources and storage energy systems into the smart grid. It attracted attention in industrial applications as they can handle high power and high voltage with an inherent feature of superior output voltage waveform quality. Moreover, its variant, the switched-capacitor MLI (SCMLI), has the added benefit of lesser DC supply requirement. In this paper, a switched-capacitor multilevel inverter topology has been proposed, which can operate in symmetric and asymmetric mode. The proposed SCMLI generate thirteen and thirty-one level output voltages for symmetric and asymmetric selection of DC voltage sources, respectively. The proposed SCMLI has a smaller number of switching devices for a given output voltage level as compared to other recently proposed topologies. A thorough comparison is presented with the recently proposed topologies on several parameters, including cost function. To validate the proposed topology, symmetric and asymmetric cases were simulated using Matlab® 2018a and the results were verified using an experimental hardware setup.
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 07-2022
Publisher: Wiley
Date: 31-07-2022
DOI: 10.1002/CTA.3391
Abstract: A High Gain High‐Level switched‐capacitor multilevel inverter with low voltage stress requires a lower number of devices at peak output voltage and a reduced number of circuit components along with an increase in voltage boosting capability. The features of the proposed topology include inherent boosting (Gain: 3) and self‐voltage balancing properties. To avoid complex algorithms, calculations and obtain superior quality output voltage the nearest level control (NLC) modulation technique is used. The extension of the topology has also been derived for the higher voltage gain and levels by adding four switches and one capacitor. The proposed topology has been compared with the recently developed topologies. The power loss analysis and simulation analysis has been done with different loading conditions under the environment of PLECS 4.2.18 and MATLAB® 2018a, respectively. A hardware bench has been set up to show the verification of the simulation results with hardware results.
Publisher: Hindawi Limited
Date: 21-10-2021
Publisher: Institution of Engineering and Technology (IET)
Date: 09-01-2020
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 12-2020
Publisher: IEEE
Date: 03-2018
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 11-2022
Publisher: IEEE
Date: 10-2019
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2019
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2019
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2019
Publisher: Institution of Engineering and Technology (IET)
Date: 12-2020
Publisher: Institution of Engineering and Technology (IET)
Date: 02-04-2020
Publisher: Hindawi Limited
Date: 07-01-2021
Publisher: Wiley
Date: 23-03-2021
DOI: 10.1002/CTA.3004
Abstract: This paper proposes a new switched‐capacitor nine‐level (9L) inverter with reduced switch count. In the proposed topology, floating capacitor (FC) is employed as a voltage booster, and it does not need any additional sensors to maintain the voltage across the FC. Due to additional FC, the number of dc sources and voltage stress on switches is reduced. Moreover, the proposed topology can be cascaded to achieve more voltage levels. Various parameters are considered in the comparison of the proposed topology with other recent switched‐capacitor topologies. Simulation and experimental results demonstrate the performance with different load and modulation index variations.
Publisher: IEEE
Date: 09-2019
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 12-2022
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2020
Publisher: Institution of Engineering and Technology (IET)
Date: 20-04-2021
DOI: 10.1049/PEL2.12121
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2021
Publisher: IEEE
Date: 11-10-2020
Publisher: Institution of Engineering and Technology (IET)
Date: 06-06-2022
DOI: 10.1049/PEL2.12317
Abstract: With the advancement of the application of power converters in the power industry, the research towards the prominent power converter namely multilevel inverter has gained a lot of attraction. Here, a dual‐source configured 11 level inverter topology is being discussed, which uses nine power semiconductor devices and one capacitor. The proposed topology is able to charge the capacitor up to 2 V dc which provides the boosting feature with the voltage gain of 1.67. An extended comparison with several other topologies has been provided which highlights the major contribution of the work. A low‐power laboratory prototype has been used for the validation of the proposed 11 level topology. Further, a thorough assessment of comparable topologies has been conferred in detail.
Publisher: MDPI AG
Date: 03-08-2021
DOI: 10.3390/EN14154709
Abstract: The component count for the multilevel inverter has been a research topic for the last few decades. The higher number of power semiconductor devices and sources leads to a higher power loss with the complex control requirement. A new multilevel inverter topology employing the concept of half-Bridge modules is suggested in this paper. It requires a lower number of dc sources and power components. The inverter is controlled using a fundamental frequency switching scheme. With the basic unit being able to produce 13 level voltage waveforms with three dc voltage sources, higher-level inverter configuration has also been discussed in the paper. The performance of the topology is analyzed in the aspects of circuit parameters and found better when compared to similar topologies proposed in recent literature. The comparison provided in the paper set the benchmark of the proposed topology in terms of lower component requirements. The topology is also optimized with two voltage fixing algorithms for maximizing the number of levels for the given number of IGBTs, drivers and dc sources, and the observations are presented. The efficiency analysis gives the peak efficiency as 98.5%. The simulations were carried out using the PLECS software tool and validated using a prototype rated at 500 W. The results with several test conditions have been reported and discussed in the paper.
Publisher: Institution of Engineering and Technology (IET)
Date: 11-2020
Publisher: Wiley
Date: 05-04-2021
DOI: 10.1002/CTA.3014
Abstract: The research on the multilevel inverter structures has been focused on reducing the number of voltage sources and the components while obtaining voltage boosting in the output voltage. A lesser number of components would ensure lesser cost while higher boosting ability increases its application potential. Based on these features, the paper presents a new topology for switched‐capacitor multi‐level inverter (SCMLI), which can produce an output voltage waveform of nine levels with a voltage boosting of twice the input voltage employing a single dc voltage source, three capacitors, and 11 power switches. The operation of switches, capacitors with a self‐charge balancing modulation scheme, and a voltage source for producing nine‐level boosted output voltage make this topology useful, and it is capable of supplying different types of load with efficiency above 97%. The simulation results and the hardware results are provided to verify the satisfactory operation of the proposed topology.
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2023
Publisher: Elsevier BV
Date: 06-2021
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2019
Publisher: Wiley
Date: 26-06-2021
DOI: 10.1002/CTA.3091
Abstract: Multilevel inverters (MLI) have become an integral component in many industrial applications including drive systems and distributed generation grid integrated systems. Efficient and cost‐effective MLI topologies are required to enhance the performance of industrial systems. In the present work, an asymmetric double H‐bridge MLI is proposed, which incorporates and enhances the attributes of a modified T‐type converter and produces a superior output voltage waveform with the lesser component requirement. The proposed MLI can generate a 15‐level output. An extendable generalized topology (cascaded) based on the proposed configuration has also been proposed. The topology is compared with recently introduced MLI topologies based on various performance parameters, and results are presented. The output voltage control is achieved using nearest level control which is a low switching frequency modulation technique for lowering the switching losses in the inverter. The hardware is realized, and performance is evaluated under different dynamically changing loading conditions.
Publisher: MDPI AG
Date: 13-05-2019
DOI: 10.3390/EN12091810
Abstract: Multilevel inverters are proficient in achieving a high-quality staircase output voltage waveform with a lower amount of harmonic content. In this paper, a new hybrid multilevel inverter topology based on the T-type and H-bridge module is presented. The proposed topology aims to achieve a higher number of levels utilizing a lower number of switches, direct current (dc) voltage sources, and voltage stresses across different switches. The basic unit of the proposed single T-type and double H-bridge multilevel inverter (STDH-MLI) produces 15 levels at the output using three dc voltage sources. The proposed topology can be extended by connecting a larger number of dc voltage sources in the T-type section. The nearest level control (NLC) switching technique is used to generate gate pulses for switches to achieve a high-quality output voltage waveform. In addition, a simplified way to achieve NLC is also described in the paper. A detailed comparison with other similar topologies is provided to set the benchmark of the proposed topology. Finally, experimental work is carried out to validate the performance of the proposed topology.
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 05-2021
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2020
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 04-2021
Publisher: Institution of Engineering and Technology (IET)
Date: 11-2020
Publisher: Informa UK Limited
Date: 21-11-2022
Publisher: Institution of Engineering and Technology (IET)
Date: 21-09-2020
Publisher: IEEE
Date: 02-10-2020
Publisher: Wiley
Date: 09-02-2021
DOI: 10.1002/CTA.2971
Publisher: Informa UK Limited
Date: 31-07-2022
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 07-2020
Publisher: IEEE
Date: 12-2018
Publisher: Springer Science and Business Media LLC
Date: 25-05-2020
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 02-2022
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 08-2022
Publisher: Hindawi Limited
Date: 15-09-2020
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date: 2020
Publisher: Institution of Engineering and Technology (IET)
Date: 11-2020
Publisher: IEEE
Date: 10-2019
No related grants have been discovered for Marif Daula Siddique.