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Research Topic : Logic
Field of Research : Integrated Circuits
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  • Funded Activity

    Linkage Projects - Grant ID: LP0212905

    Funder
    Australian Research Council
    Funding Amount
    $180,998.00
    Summary
    Design and Formal Verification of Control and Data Acquisition Protocols. This research will develop new specification and verification techniques for remote control protocols, used among interconnected sites in supply utilities such as electricity grids, based on a proven formal methods technology. These protocols are used in the monitoring of data from remote sites, and the transmission of control commands to such sites from a central location. Benefits to the industrial partner include increa .... Design and Formal Verification of Control and Data Acquisition Protocols. This research will develop new specification and verification techniques for remote control protocols, used among interconnected sites in supply utilities such as electricity grids, based on a proven formal methods technology. These protocols are used in the monitoring of data from remote sites, and the transmission of control commands to such sites from a central location. Benefits to the industrial partner include increased assurance that their control technology does correctly realise the adopted protocols. Assurance of correctness is significant in that incorrect protocol implementation may cause errant operation of equipment, and lead to economic and environmental damage.
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    Funded Activity

    Discovery Projects - Grant ID: DP0559582

    Funder
    Australian Research Council
    Funding Amount
    $160,000.00
    Summary
    RNS Hardware for Public-Key Cryptography and E-security. In a world where electronic communication is ever-present, the security of electronic information, e-security, is an issue of the utmost concern for government, business and individuals alike. Public-key cryptography is a powerful tool in the e-security toolkit. Using this technology it is possible to confirm the identity of individuals, maintain the privacy of personal data and guarantee the authenticity of transactions. The aim of this .... RNS Hardware for Public-Key Cryptography and E-security. In a world where electronic communication is ever-present, the security of electronic information, e-security, is an issue of the utmost concern for government, business and individuals alike. Public-key cryptography is a powerful tool in the e-security toolkit. Using this technology it is possible to confirm the identity of individuals, maintain the privacy of personal data and guarantee the authenticity of transactions. The aim of this project is to design new public-key cryptography hardware to provide faster, more secure communications for computers, networks and smart cards. Achieving this will require innovations in the way computers perform arithmetic and how this arithmetic is realised as an integrated circuit.
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    Funded Activity

    Linkage - International - Grant ID: LX0239968

    Funder
    Australian Research Council
    Funding Amount
    $31,100.00
    Summary
    Simulation and verification of system-level specifications of requirements and constraints using Rosetta. Modern computer-based systems comprise a mixture of electronic hardware and embedded computer software that interacts with mechanical and other non-electrical subsystems. Future design capability will depend on being able to model the requirements and constraints of heterogeneous systems, so that they can be simulated and formally verified before being manufactured and deployed. This project .... Simulation and verification of system-level specifications of requirements and constraints using Rosetta. Modern computer-based systems comprise a mixture of electronic hardware and embedded computer software that interacts with mechanical and other non-electrical subsystems. Future design capability will depend on being able to model the requirements and constraints of heterogeneous systems, so that they can be simulated and formally verified before being manufactured and deployed. This project will develop techniques and software tools for simulation and verification based on the new Rosetta system-level design language. These tools will make the design of complex computer-based systems faster, more reliable and less costly by minimizing design errors early in the design flow.
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    Funded Activity

    Discovery Projects - Grant ID: DP0211387

    Funder
    Australian Research Council
    Funding Amount
    $222,932.00
    Summary
    Smart CMOS Vision Sensors in Deep Sub-0.25um CMOS Technologies. This research project aims to develop a new generation of smart vision sensors featuring on-chip and pixel-level implementation of human vision based algorithms. Built in state-of-the-art deep sub-0.25um CMOS technologies, these imagers will feature extensive in-pixel processing power in contrast to the currently commercially available CMOS vision sensors. This will enable on-chip vision-based decision making but also increased on-c .... Smart CMOS Vision Sensors in Deep Sub-0.25um CMOS Technologies. This research project aims to develop a new generation of smart vision sensors featuring on-chip and pixel-level implementation of human vision based algorithms. Built in state-of-the-art deep sub-0.25um CMOS technologies, these imagers will feature extensive in-pixel processing power in contrast to the currently commercially available CMOS vision sensors. This will enable on-chip vision-based decision making but also increased on-chip image processing. These innovative system-on-chip features will contribute towards the positioning of CMOS imaging technology as the technology of choice for most digital imaging applications, in place of the existing, and so far unchallenged, CCD technology.
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    Funded Activity

    Discovery Projects - Grant ID: DP0881219

    Funder
    Australian Research Council
    Funding Amount
    $645,000.00
    Summary
    Electronic Auditory Pathway. We will develop electronic building blocks to investigate biological signal processing. In particular, we will investigate the auditory pathway and develop the most accurate electronic model of the biological cochlea and auditory nerve. These will be followed by electronic circuits that model the processing of sensory signals in the brain. Processing signals with neural spikes offers distinct advantages over current analogue and digital signal processing techniques i .... Electronic Auditory Pathway. We will develop electronic building blocks to investigate biological signal processing. In particular, we will investigate the auditory pathway and develop the most accurate electronic model of the biological cochlea and auditory nerve. These will be followed by electronic circuits that model the processing of sensory signals in the brain. Processing signals with neural spikes offers distinct advantages over current analogue and digital signal processing techniques in terms of noise, energy consumption and extraction of temporal information. We will implement the first spike-based models of pitch and timbre perception, and a neural model of speech recognition in noisy environments.
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    Funded Activity

    Discovery Projects - Grant ID: DP0211608

    Funder
    Australian Research Council
    Funding Amount
    $196,000.00
    Summary
    A 3D CMOS Vision Sensor with Pixel Level Analog-to-Digital Converter and Intelligent Processing. The aim of this research project is to build a smart vision sensor using advanced 3D technology. The smart sensor will consist of two vertically stacked levels comprising the vision sensor chip with pixel-level Analog-to-Digital Converter (ADC) and the processing chip for edge and motion detection. The pixel level ADC will be based on new architectures offering improved performance in terms of dynami .... A 3D CMOS Vision Sensor with Pixel Level Analog-to-Digital Converter and Intelligent Processing. The aim of this research project is to build a smart vision sensor using advanced 3D technology. The smart sensor will consist of two vertically stacked levels comprising the vision sensor chip with pixel-level Analog-to-Digital Converter (ADC) and the processing chip for edge and motion detection. The pixel level ADC will be based on new architectures offering improved performance in terms of dynamic range, fill-factor, and signal-to-noise ratio. Both the vision and the processing chips will be realised in standard CMOS technology, which make the smart vision sensor very suitable for low cost consumer electronic applications.
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